September 2025
HW Design Engineer
INTERA is a dynamic company at the forefront of IoT research and development, dedicated to bringing innovative real-time monitoring and management solutions to market. We actively engage in cutting-edge national and international collaborative R&D initiatives spanning various domains, including Energy, Health, and Computing.
We are currently offering an exciting opportunity for a highly skilled and experienced engineer. This role is pivotal within our new R&D unit, which is exclusively dedicated to Edge Computing. We are seeking an individual with a deep understanding of co-processor development based on the RISC-V architecture, specifically tailored for Artificial Intelligence applications on ultra-low-power devices. In this role, your primary responsibilities will revolve around the development of RTL netlist coding and implementation in FPGA. You will be instrumental in conducting design-space exploration, deftly navigating the intricate trade-offs between resource utilization, performance optimization, and power efficiency. Join us in pioneering the future of Edge Computing, where your expertise will play a crucial role in shaping the landscape of IoT innovation.
INTERA is a company that brings R&D around IoT to the market, providing innovative real-time monitoring and management solutions, and being involved in state-of-the-art national and international collaborative R&D projects in areas such as Energy, Health, and Computing.
We currently have an exciting opportunity for a technically capable experienced engineer. For the new R&D unit devoted to Edge Computing, we are looking for a profile with the knowledge to develop co-processors based on RISC-V architecture and targeted to Artificial Intelligence applications in ultra-low-power devices. This person will focus on developing RTL netlist coding and implementation in a FPGA, performing design-space exploration and taking care of the trade-off between resource usage, performance, and power consumption.
For the position, the candidate will be engaged in the following activities:
- Development and implementation of generic HW accelerators.
- RTL Design, debugging and verification.
- Integration of HW accelerators (memory mapped and custom instructions) on RISC-V.
- RISC-V firmware/driver development (Embedded C) to test HW accelerators.
- FPGA prototyping with EDA tools and platforms such as Xilinx/Altera or similar.
Skills:
- PhD/BS/MS in Engineering with emphasis in Digital Design.
- Advanced knowledge of at least one Hardware Description Language, preferably System Verilog.
- Experience with HW simulators and synthesis tools.
- Good knowledge of modern CPU architectures (preferably RISC-V) and micro-architectures.
- Knowledge on the base and extensions of the RISC-V instruction set.
- Embedded C for driver and firmware development.
- Excellent written/verbal communication skills and strong teamwork/collaboration.
Other desirable skills:
- Open-source development tools experience: Linux, GitHub, Makefiles, Python, etc.
- AI theoretical/practical knowledge.
- RTOS and Embedded Linux experience.
- Knowledge and experience working through the ASIC Digital Design Flow: specifications definition, RTL verification, synthesis, power estimation.
- UVM theoretical/practical knowledge.
INTERA actively fosters an environment to facilitate and strengthen gender equality, diversity, and inclusion in selecting, hiring, remunerating and promoting its employees. The company also balances on-site and remote work according to personal and professional requirements.
